In the existing semiconductor package designs, the crosstalk induced by socket pins is one of the most important bottlenecks in achieving electrical performance for the interconnect(s) on the package. One current solution is to carefully design the package pin map to isolate the high speed signals from their neighbors, e.g., by using a relatively large number of Vss pins to separate byte lanes and channels. However, the crosstalk from the socket pin could still easily reach a value that would outweigh such crosstalk reduction layout efforts both on package and motherboard. In addition, adding more Vss pins on the pin map will result in package size growth and/or cost increase.